Lenovo 3000 N220-N440-Wistron ...

Lenovo 3000 N220-N440-Wistron Anote2.0 AMD, LENOVO IBM

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5
4
3
2
1
A-NOTE 2.0 Block Diagram
PCB Layer Stackup
L1: Signal 1
L2: VCC
L3: Inner Signal 2
L4: Inner Signal 3
L5: GND
L6: Signal 4
Project Code:91.4T001.001
Layers:6
PCB P/N: 06235-SA
D
D
DDRII
667/800
AMD CPU
DDRII 800M Channel A
Slot 0
NPT Processor
Rev. G
S1 package
CLK GEN
VGA_CORE_S0
Battery Charger
ICS951412
49
44
ISL6268
ISL6255
DDRII 800M Channel B
DDRII
667/800
Slot 1
INPUTS
OUTPUTS
INPUT
DCBATOUT
OUTPUT
3
4,5,6,7
8,9
VGA_CORE_S0
AD+
BAT+
DCBATOUT
VRAM
HyperTransport
6.4GB/S 16b/8b
54,55
SYSTEM DC/DC
S-VIDEO
TV-OUT
TPS 51120
OUTPUT
41
PCI-E 1X
14
INPUT
MINI-CARD
X16
ATI M71
DCBATOUT
5V_S5
3D3V_S5
27
ATI
Discrete
LVDS
LCD
NEW CARD
PCI-E 1X
15
RS690MC/RX690
C
27
50,51,52,53
SYSTEM DC/DC
C
APL5332KAC
18
AGTL+ CPU I/F
UMA
INPUT
OUTPUT
10/100Mb/1G
PCI-E 1X
10,11,12,13
RGB CRT
PCIE LAN
BroadCom
BCM5906M/
BCM5787M
10/100/1G
CRT
14
3D3V_S5
1D2V_S5
RJ45
26
TXFM
26
SYSTEM POWER
PCI-Express
x4
Digital Camer
15
TPS51116
42
INPUT
OUTPUT
TXFM
26
Finger Print
22
Bluetooth
22
DCBATOUT
1D8V_S3
0D9V_S3
25,26
RJ11
CONN
USB x
4
1D2V_S0
10xUSB 2.0
43
HD AUDIO
22
ISL6268
CX20548
ATI
SB600
ACPI 2.0
INPUT
DCBATOUT
OUTPUT
1D2V_S0
AZALIA HD
AZALIA
B
B
MAX4411
29
HeadPhone
MIC IN
HD AUDIO
CODEC
CPU V_CORE
PCI Bus / 33MHz
SD/MMC/MS/
MS-PRO/XD/SM
Card Slot
PCI
38,39
RICOH
INTERNAL
MIC
CX20549-12Z
ISL6264
OP AMP
R5C832
28
INPUT
OUTPUT
APA2031
29
Cardbus
LPC Bus / 33MHz
DCBATOUT
71.SB600.A0U
VCC_CORE_S0
24
LPC I/F
ATA 133
16,17,18,19,20
2CH
SPEAKER
SYSTEM POWER
TPS 51120
1394
41
Thermal
& Fan
G792
KBC
WPC8765
24
SPI
INPUT
OUTPUT
23,24
21
5V_AUX_S5
30
DCBATOUT
3D3V_AUX_S5
<Core Design>
<Core Design>
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
DVD/
CD-RW
HDD
SPI ROM
Debug(GF)
33
4M bit
Touch
Pad
Int.
KB
Title
Title
Title
34
34
31
G-SENSOR
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
31
32
32
A3
A3
A3
SA
SA
SA
A-NOTE2.0-AMD
A-NOTE2.0-AMD
A-NOTE2.0-AMD
Date:
Date:
Date:
Tuesday, September 26, 2006
Tuesday, September 26, 2006
Tuesday, September 26, 2006
Sheet
Sheet
Sheet
1
1
1
of
of
of
55
55
55
5
4
3
2
1
 5
4
3
2
1
SA: 07/31/06 Start
D
D
C
C
B
B
<Core Design>
<Core Design>
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CHANGE HISTORY
CHANGE HISTORY
CHANGE HISTORY
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
SA
SA
SA
A-NOTE2.0-AMD
A-NOTE2.0-AMD
A-NOTE2.0-AMD
Date:
Date:
Date:
Tuesday, September 26, 2006
Tuesday, September 26, 2006
Tuesday, September 26, 2006
Sheet
Sheet
Sheet
2
2
2
of
of
of
55
55
55
5
4
3
2
1
 A
B
C
D
E
CLK_PCIE_NEW#
CLK_PCIE_NEW
R305
R305
49D9R2F-GP
49D9R2F-GP
1
2
R304
R304
49D9R2F-GP
49D9R2F-GP
1
2
SBLINK_CLK#
SBLINK_CLK
SBSRC_CLK#
SBSRC_CLK
NBSRC_CLK#
NBSRC_CLK
R243
R243
49D9R2F-GP
49D9R2F-GP
1
2
R242
R242
49D9R2F-GP
49D9R2F-GP
1
2
4
4
1
2
R309
R309
49D9R2F-GP
49D9R2F-GP
1
2
R308
R308
49D9R2F-GP
49D9R2F-GP
R245
R245
49D9R2F-GP
49D9R2F-GP
1
2
R244
R244
49D9R2F-GP
49D9R2F-GP
1
2
CLK_PCIE_MINI#
CLK_PCIE_MINI
R311
R311
49D9R2F-GP
49D9R2F-GP
2
3
4
1
2
SBLINK_CLK#
12
RN40
RN40
1
SBLINK_CLK
12
3D3V_CLK_VDDA
SRN33J-5-GP-U
SRN33J-5-GP-U
R310
R310
49D9R2F-GP
49D9R2F-GP
1
2
CLK_PCIE_LAN#
CLK_PCIE_LAN
CLK_PCIE_GFX#
CLK_PCIE_GFX
R303
R303
49D9R2F-GP
49D9R2F-GP
1
2
4
1
2
SBSRC_CLK#
16
3D3V_S0
3D3V_CLK_VDD
RN45
RN45
SRN33J-5-GP-U
SRN33J-5-GP-U
3
SBSRC_CLK
16
U33
U33
R302
R302
49D9R2F-GP
49D9R2F-GP
1
2
R290
R290
3D3VDD48_S0
SRC_CLK0#
SRC_CLK0
SRC_CLK3#
SRC_CLK3
SRN33J-5-GP-U
SRN33J-5-GP-U
R307
R307
49D9R2F-GP
49D9R2F-GP
1
2
3
33
1
2
4
1
2
CLK_PCIE_GFX#
50
VDD48
SRCCLKC0
VGA
VGA
RN44
RN44
39
34
3
CLK_PCIE_GFX
50
VDDA
SRCCLKT0
0R3-0-U-GP
0R3-0-U-GP
R306
R306
49D9R2F-GP
49D9R2F-GP
32
25
1
2
VDDATI
SRCCLKC3
C483
SC2D2U16V5ZY-2GP
24
SRCCLKT3
PCIE_GFX_CLK#
PCIE_NEW_CLK#
PCIE_NEW_CLK
SRN33J-5-GP-U
SRN33J-5-GP-U
21
23
1
2
4
CLK_PCIE_NEW#
27
VDDSRC
SRCCLKC4
PCIE_GFX_CLK
RN43
RN43
14
22
3
CLK_PCIE_NEW
27
VDDSRC
SRCCLKT4
35
19
VDDSRC
SRCCLKC5
18
SRCCLKT5
56
17
PCIE_LAN_CLK#
PCIE_LAN_CLK
1
2
4
SRN33J-5-GP-U
SRN33J-5-GP-U
VDDREF
SRCCLKC6
CLK_PCIE_LAN#
25
51
16
RN42
RN42
3
VDDPCI
SRCCLKT6
CLK_PCIE_LAN
25
1
2
C470
SC33P50V2JN-3GP
XI_CLK
43
13
CPUCLK#
6
VDDCPU
SRCCLKC7
48
12
VDDHTT
SRCCLKT7
3
3
R263
DUMMY-R3
DY
R254
261R2F-GP
40
CPUCLK8C1
X4
X-14D318MHZ-18GP
1
41
X1
CPUCLK8T1
CPUCLKJ_CY
CPUCLK_CY
R258
R258
47R2J-2-GP
47R2J-2-GP
Nea
r
To CLKGEN
2
44
1
2
X2
CPUCLK8C0
R257
R257
47R2J-2-GP
47R2J-2-GP
45
1
2
CPUCLK
6
CPUCLK8T0
USB_48M
SMBC_CLK
SMBD_CLK
4
USB_48MHZ
C468
SC33P50V2JN-3GP
XO_CLK
RN41
RN41
1
2
7
SCLK
ATI_CLK0#
ATI_CLK0
8
29
2
3
4
NBSRC_CLK#
12
SDATA
ATIGCLKC0
30
1
NBSRC_CLK
12
ATIGCLKT0
33R2F-3-GP
33R2F-3-GP
R280
R280
CLK_REQA#
SRN33J-5-GP-U
SRN33J-5-GP-U
1
2
10
28
19
CLK48_USB
CLKREQA#
ATIGCLKC1
SRN33J-5-GP-U
SRN33J-5-GP-U
CLK_REQB#
MINICARD_CLK#
MINICARD_CLK
11
27
1
2
4
CLK_PCIE_MINI#
27
8,19
SMBC0_SB
CLKREQB#
ATIGCLKT1
3
CLK_PCIE_MINI
27
8,19
SMBD0_SB
RN46
RN46
TPAD30
TPAD30
TP56
TP56
FS2
FS1
9
36
FS2
GNDSRC
33R2F-3-GP
33R2F-3-GP
R252
R252
R300
R300
3D3V_CLK_VDD
1
2
53
20
12
CLK14_NB
FS1/REF1
GNDSRC
33R2F-3-GP
33R2F-3-GP
R247
R247
FS0
1
2
54
15
1
2
12,19
SB_OSC_CLK
FS0/REF0
GNDSRC
26
GNDSRC
10KR2J-3-GP
DY
10KR2J-3-GP
DY
52
REF2
42
GNDCPU
12
HTREF_CLK
33R2F-3-GP
33R2F-3-GP
R256
R256
CLK_HTT66
R301
0R2J-2-GP
1
2
47
49
HTTCLK0
GNDPCI
3D3V_S0
3D3V_CLK_VDD
50
46
PCICLK0
GNDHTT
31
for IDTCV137PAG testing
L27
L27
GNDATI
IREF_CLKGEN
37
38
1
2
IREF
GNDA
5
GND
6
55
BLM11A601S-N1
BLM11A601S-N1
NC#6
GND
DY
C488
SC1000P50V2JN-GP
DY
DY
DY
C486
SC1000P50V2JN-GP
R253
49D9R2F-GP
R241
475R2F-L1-GP
C484
SCD1U16V2ZY-2GP
C451
SCD1U16V2ZY-2GP
C450
SCD1U16V2ZY-2GP
C462
C462
C453
SC22U10V6ZY-2GP
C488
SC1000P50V2JN-GP
C486
SC1000P50V2JN-GP
for ICS951412(71.95142.B0W)
CY28RS480
IDTCV137PAG(71.00137.C0W)
ICS951412AGLFT-GP
ICS951412AGLFT-GP
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
2
2
3D3V_S0
Pin 9 CY28RS480 is NC
C447
SCD1U16V2ZY-2GP
C446
SCD1U16V2ZY-2GP
C448
SCD1U16V2ZY-2GP
C487
SCD1U16V2ZY-2GP
DY
DY
DY
DY
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
R297
R297
R298
R298
0R2J-2-GP
0R2J-2-GP
D
Y
DY
R296
R296
CLK_REQA#
CLK_REQB#
1
2
27
NEWCARD_CLKREQ#
3D3V_CLK_VDDA
3D3V_S0
0R2J-2-GP
0R2J-2-GP
R299
R299
1
DY
DY
2
25
LAN_CLKREQ#
L26
L26
1
2
BLM11A601S-N1
BLM11A601S-N1
for ICS951412
C449
SCD1U16V2ZY-2GP
C452
C452
C458
SC22U10V6ZY-2GP
DY
3D3V_CLK_VDD
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
R248
R248
2K2R2J-2-GP
2K2R2J-2-GP
FS0
FS2
FS1
FS0
CPU
HTT
PCI
1
2
R249
DUMMY-R2
R249
DUMMY-R2
MHz
MHz
MHz
1
2
DY
DY
0
0
0
0
Hi-Z
Hi-Z
Hi-Z
R251
R251
2K2R2J-2-
G
P
2K2R2J-2-GP
FS1
0
1
X
X/3
X/6
1
2
<Core Design>
<Core Design>
<Core Design>
1
1
R250
DUMMY-R2
R250
DUMMY-R2
0
1
0
180.00
60.00
30.00
1
2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
DY
DY
0
1
1
220.00
73.12
36.56
R283
R283
2K2R2J-2-GP
2K2R2J-2-GP
FS2
1
0
0
100.00
66.66
33.33
1
2
R282
DUMMY-R2
R282
DUMMY-R2
1
0
1
133.33
66.66
33.33
Title
Title
Title
1
2
CLKGEN_ICS951412
CLKGEN_ICS951412
CLKGEN_ICS951412
DY
DY
1
1
1
200.00
66.66
33.33
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
A-NOTE2.0-AMD
A-NOTE2.0-AMD
A-NOTE2.0-AMD
SA
SA
SA
Date:
Date:
Date:
Tuesday, September 26, 2006
Tuesday, September 26, 2006
Tuesday, September 26, 2006
Sheet
Sheet
Sheet
3
3
3
of
of
of
55
55
55
A
B
C
D
E
 A
B
C
D
E
4
4
U66A
U66A
NB0HTTCLKOUT1
NB0HTTCLKOUT0
NB0HTTCLKOUTJ0
CPUHTTCLKOUT1
CPUHTTCLKOUTJ1
J5
Y4
CPUHTTCLKOUT1
10
10
NB0HTTCLKOUT1
L0_CLKIN_H1
L0_CLKOUT_H1
NB0HTTCLKOUTJ1
K5
Y3
CPUHTTCLKOUTJ1
10
10
NB0HTTCLKOUTJ1
L0_CLKIN_L1
L0_CLKOUT_L1
R226
51R2J-2-GP
CPUHTTCLKOUT0
J3
Y1
CPUHTTCLKOUT0
10
10
NB0HTTCLKOUT0
L0_CLKIN_H0
L0_CLKOUT_H0
1D2V_HT0A_S0
CPUHTTCLKOUTJ0
J2
W1
CPUHTTCLKOUTJ0
10
10
NB0HTTCLKOUTJ0
L0_CLKIN_L0
L0_CLKOUT_L0
1
2
CPUHTTCTLIN1
CPUHTTCTLINJ1
P3
T5
L0_CTLIN_H1
L0_CTLOUT_H1
1
2
P4
R5
L0_CTLIN_L1
L0_CTLOUT_L1
NB0HTTCTLOUT
N1
R2
CPUHTTCTLOUT0
CPUHTTCTLOUTJ0
CPUHTTCTLOUT0
10
10
NB0HTTCTLOUT
L0_CTLIN_H0
L0_CTLOUT_H0
NB0HTTCTLOUTJ
P1
R3
CPUHTTCTLOUTJ0
10
10
NB0HTTCTLOUTJ
L0_CTLIN_L0
L0_CTLOUT_L0
51R2J-2-GP
51R2J-2-GP
R224
3
3
R224
NB0CADOUT15
CPUCADOUT15
N5
T4
CPUCADOUT[15..0]
10
10
NB0CADOUT[15..0]
L0_CADIN_H15
L0_CADOUT_H15
NB0CADOUTJ15
CPUCADOUTJ15
P5
T3
CPUCADOUTJ[15..0]
10
10
NB0CADOUTJ[15..0]
L0_CADIN_L15
L0_CADOUT_L15
NB0CADOUT14
NB0CADOUT13
NB0CADOUT12
NB0CADOUT11
CPUCADOUT14
M3
V5
L0_CADIN_H14
L0_CADOUT_H14
NB0CADOUTJ14
CPUCADOUTJ14
M4
U5
L0_CADIN_L14
L0_CADOUT_L14
CPUCADOUT13
L5
V4
L0_CADIN_H13
L0_CADOUT_H13
NB0CADOUTJ13
CPUCADOUTJ13
M5
V3
L0_CADIN_L13
L0_CADOUT_L13
CPUCADOUT12
K3
Y5
L0_CADIN_H12
L0_CADOUT_H12
NB0CADOUTJ12
CPUCADOUTJ12
K4
W5
L0_CADIN_L12
L0_CADOUT_L12
CPUCADOUT11
CPUCADOUT10
H3
AB5
L0_CADIN_H11
L0_CADOUT_H11
NB0CADOUTJ11
CPUCADOUTJ11
CPUCADOUTJ10
H4
AA5
L0_CADIN_L11
L0_CADOUT_L11
NB0CADOUT10
G5
AB4
L0_CADIN_H10
L0_CADOUT_H10
NB0CADOUTJ10
H5
AB3
L0_CADIN_L10
L0_CADOUT_L10
NB0CADOUT9
NB0CADOUT8
CPUCADOUT9
F3
AD5
L0_CADIN_H9
L0_CADOUT_H9
NB0CADOUTJ9
NB0CADOUTJ8
CPUCADOUTJ9
F4
AC5
L0_CADIN_L9
L0_CADOUT_L9
CPUCADOUT8
E5
AD4
L0_CADIN_H8
L0_CADOUT_H8
CPUCADOUTJ8
F5
AD3
L0_CADIN_L8
L0_CADOUT_L8
HYPERTRANSPORT
HYPERTRANSPORT
NB0CADOUT7
CPUCADOUT7
N3
T1
L0_CADIN_H7
L0_CADOUT_H7
NB0CADOUTJ7
CPUCADOUTJ7
N2
R1
L0_CADIN_L7
L0_CADOUT_L7
NB0CADOUT6
CPUCADOUT6
CPUCADOUT5
L1
U2
L0_CADIN_H6
L0_CADOUT_H6
NB0CADOUTJ6
M1
U3
CPUCADOUTJ6
CPUCADOUTJ5
L0_CADIN_L6
L0_CADOUT_L6
NB0CADOUT5
L3
V1
L0_CADIN_H5
L0_CADOUT_H5
NB0CADOUTJ5
NB0CADOUT4
L2
U1
L0_CADIN_L5
L0_CADOUT_L5
J1
W2
CPUCADOUT4
L0_CADIN_H4
L0_CADOUT_H4
NB0CADOUTJ4
CPUCADOUTJ4
K1
W3
L0_CADIN_L4
L0_CADOUT_L4
NB0CADOUT3
CPUCADOUT3
G1
AA2
L0_CADIN_H3
L0_CADOUT_H3
NB0CADOUTJ3
CPUCADOUTJ3
H1
AA3
L0_CADIN_L3
L0_CADOUT_L3
NB0CADOUT2
CPUCADOUT2
G3
AB1
L0_CADIN_H2
L0_CADOUT_H2
2
2
NB0CADOUTJ2
CPUCADOUTJ2
G2
AA1
L0_CADIN_L2
L0_CADOUT_L2
NB0CADOUT1
NB0CADOUTJ1
CPUCADOUT1
E1
AC2
L0_CADIN_H1
L0_CADOUT_H1
CPUCADOUTJ1
F1
AC3
L0_CADIN_L1
L0_CADOUT_L1
NB0CADOUT0
CPUCADOUT0
E3
AD1
L0_CADIN_H0
L0_CADOUT_H0
NB0CADOUTJ0
CPUCADOUTJ0
E2
AC1
L0_CADIN_L0
L0_CADOUT_L0
62.10055.111
62.10055.111
<Core Design>
<Core Design>
<Core Design>
1
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU(1/4)_HyperTransport I/F
CPU(1/4)_HyperTransport I/F
CPU(1/4)_HyperTransport I/F
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
SA
SA
SA
A-NOTE2.0-AMD
A-NOTE2.0-AMD
A-NOTE2.0-AMD
Date:
Date:
Date:
Tuesday, September 26, 2006
Tuesday, September 26, 2006
Tuesday, September 26, 2006
Sheet
Sheet
Sheet
4
4
4
of
of
of
55
55
55
A
B
C
D
E
 A
B
C
D
E
U66C
U66C
4
4
AF18
MB0_CLK_H2
M_B_CLK_DDR2
8
AF17
8
M_B_DQ[63..0]
M_B_CLK_DDR2#
8
MB0_CLK_L2
M_B_DQ63
AD11
A17
M_B_CLK_DDR1
8
MB_DATA63
MB0_CLK_H1
M_B_DQ62
M_B_DQ60
AF11
A18
M_B_CLK_DDR1#
8
MB_DATA62
MB0_CLK_L1
M_B_DQ61
AF14
MB_DATA61
AE14
Y26
M_B_CS3#
8,9
MB_DATA60
MB0_CS_L3
U66B
U66B
M_B_DQ59
Y11
J24
M_B_CS2#
8,9
MB_DATA59
MB0_CS_L2
M_B_DQ58
M_B_DQ56
AB11
W24
M_B_CS1#
8,9
MB_DATA58
MB0_CS_L1
M_B_DQ57
Y16
AC12
U23
M_A_CLK_DDR2
8
M_B_CS0#
8,9
MA0_CLK_H2
MB_DATA57
MB0_CS_L0
AA16
AF13
8
M_A_DQ[63..0]
M_A_CLK_DDR2#
8
MA0_CLK_L2
MB_DATA56
M_A_DQ63
M_B_DQ55
AA12
E16
AF15
W23
M_A_CLK_DDR1
8
M_B_ODT1
8,9
MA_DATA63
MA0_CLK_H1
MB_DATA55
MB0_ODT1
M_A_DQ62
M_B_DQ54
M_B_DQ52
AB12
F16
AF16
W26
M_A_CLK_DDR1#
8
M_B_ODT0
8,9
MA_DATA62
MA0_CLK_L1
MB_DATA54
MB0_ODT0
M_A_DQ61
M_B_DQ53
AA14
AC18
MA_DATA61
MB_DATA53
M_A_DQ60
AB14
V19
AF19
V26
M_A_CS3#
8,9
M_B_CAS#
8,9
MA_DATA60
MA0_CS_L3
MB_DATA52
MB_CAS_L
M_A_DQ59
M_B_DQ51
W11
J22
AD14
U22
M_A_CS2#
8,9
M_B_WE#
8,9
MA_DATA59
MA0_CS_L2
MB_DATA51
MB_WE_L
M_A_DQ58
M_A_DQ56
M_B_DQ50
M_B_DQ48
Y12
V22
AC14
U24
M_A_CS1#
8,9
M_B_RAS# 8,9
M_B_BS#2 8,9
MA_DATA58
MA0_CS_L1
MB_DATA50
MB_RAS_L
M_A_DQ57
M_B_DQ49
AD13
T19
AE18
M_A_CS0#
8,9
MA_DATA57
MA0_CS_L0
MB_DATA49
AB13
AD18
K26
MA_DATA56
MB_DATA48
MB_BANK2
M_A_DQ55
M_B_DQ47
AD15
V20
AD20
T26
M_A_ODT1
8,9
M_B_BS#1 8,9
M_B_BS#0 8,9
MA_DATA55
MA0_ODT1
MB_DATA47
MB_BANK1
M_A_DQ54
M_B_DQ46
M_B_DQ44
AB15
U19
AC20
U26
M_A_ODT0
8,9
MA_DATA54
MA0_ODT0
MB_DATA46
MB_BANK0
M_A_DQ53
M_B_DQ45
AB17
AF23
MA_DATA53
MB_DATA45
M_A_DQ52
Y17
U20
AF24
H26
M_A_CAS#
8,9
M_B_CKE1
8,9
MA_DATA52
MA_CAS_L
MB_DATA44
MB_CKE1
M_A_DQ51
M_B_DQ43
Y14
U21
AF20
J23
M_A_WE#
8,9
M_B_CKE0
8,9
MA_DATA51
MA_WE_L
MB_DATA43
MB_CKE0
M_A_DQ50
M_A_DQ48
M_B_DQ42
M_B_DQ40
W14
T20
AE20
MA_DATA50
MA_RAS_L
M_A_RAS# 8,9
M_A_BS#2 8,9
MB_DATA42
M_A_DQ49
W16
M_B_DQ41
AD22
J25
M_B_A15
MA_DATA49
MB_DATA41
MB_ADD15
AD17
K22
AC22
MEMORY
MEMORY
J26
M_B_A14
MA_DATA48
MA_BANK2
MB_DATA40
MB_ADD14
M_B_A[15..0]
8,9
M_A_DQ47
Y18
R20
M_B_DQ39
AE25
W25
M_B_A13
M_B_A12
M_B_A11
M_B_A10
M_B_A9
M_B_A8
M_B_A7
M_B_A6
M_B_A5
M_B_A4
M_B_A3
M_B_A2
M_B_A1
M_B_A0
M_B_DQS7
M_B_DQS#7
M_B_DQS6
M_B_DQS#6
M_B_DQS5
M_B_DQS#5
M_B_DQS4
M_B_DQS#4
M_B_DQS3
M_B_DQS#3
M_B_DQS2
M_B_DQS#2
M_B_DQS1
M_B_DQS#1
M_B_DQS0
M_B_DQS#0
M_B_DM7
M_B_DM6
M_B_DM5
M_B_DM4
M_B_DM3
M_B_DM2
M_B_DM1
M_B_DM0
INTERFACE
INTERFACE
M_A_BS#1 8,9
M_A_BS#0 8,9
MA_DATA47
MA_BANK1
MB_DATA39
MB_ADD13
M_A_DQ46
AD19
T22
M_B_DQ38
M_B_DQ36
AD26
L23
MA_DATA46
MA_BANK0
MB_DATA38
MB_ADD12
3
M_A_DQ45
M_B_DQ37
3
AD21
AA25
L25
MA_DATA45
MB_DATA37
MB_ADD11
M_A_DQ44
AB21
J20
AA26
U25
M_A_CKE1
8,9
MA_DATA44
MA_CKE1
MB_DATA36
MB_ADD10
M_A_DQ43
M_B_DQ35
AB18
J21
AE24
L24
M_A_CKE0
8,9
MA_DATA43
MA_CKE0
MB_DATA35
MB_ADD9
M_A_DQ42
M_A_DQ40
M_B_DQ34
M_B_DQ32
AA18
AD24
M26
MA_DATA42
MB_DATA34
MB_ADD8
M_A_DQ41
M_A_A15
M_B_DQ33
AA20
K19
AA23
L26
MA_DATA41
MA_ADD15
MB_DATA33
MB_ADD7
MEMORY
INTERFACE
MEMORY
INTERFACE
M_A_A14
Y20
K20
AA24
N23
M_A_A[15..0]
8,9
MA_DATA40
MA_ADD14
MB_DATA32
MB_ADD6
M_A_DQ39
M_A_A13
M_B_DQ31
AA22
V24
G24
N24
MA_DATA39
MA_ADD13
MB_DATA31
MB_ADD5
M_A_DQ38
M_A_A12
M_B_DQ30
M_B_DQ28
Y22
K24
G23
N25
MA_DATA38
MA_ADD12
MB_DATA30
MB_ADD4
M_A_DQ37
M_A_A11
M_B_DQ29
W21
L20
D26
N26
MA_DATA37
MA_ADD11
MB_DATA29
MB_ADD3
M_A_DQ36
M_A_A10
W22
R19
C26
P24
MA_DATA36
MA_ADD10
MB_DATA28
MB_ADD2
M_A_DQ35
M_A_A9
M_B_DQ27
AA21
L19
G26
P26
MA_DATA35
MA_ADD9
MB_DATA27
MB_ADD1
M_A_DQ34
M_A_DQ32
M_A_A8
M_B_DQ26
M_B_DQ24
AB22
L22
G25
T24
MA_DATA34
MA_ADD8
MB_DATA26
MB_ADD0
M_A_DQ33
M_A_A7
M_B_DQ25
AB24
L21
E24
MA_DATA33
MA_ADD7
MB_DATA25
M_A_A6
Y24
M19
E23
AF12
MA_DATA32
MA_ADD6
MB_DATA24
MB_DQS_H7
M_A_DQ31
M_A_A5
M_B_DQ23
H22
M20
C24
AE12
M_B_DQS[7..0]
8
MA_DATA31
MA_ADD5
MB_DATA23
MB_DQS_L7
M_A_DQ30
M_A_A4
M_B_DQ22
M_B_DQ20
H20
M24
B24
AE16
MA_DATA30
MA_ADD4
MB_DATA22
MB_DQS_H6
M_A_DQ29
M_A_A3
M_B_DQ21
E22
M22
C20
AD16
MA_DATA29
MA_ADD3
MB_DATA21
MB_DQS_L6
M_A_DQ28
M_A_A2
E21
N22
B20
AF21
M_B_DQS#[7..0]
8
MA_DATA28
MA_ADD2
MB_DATA20
MB_DQS_H5
M_A_DQ27
M_A_A1
M_B_DQ19
J19
N21
C25
AF22
MA_DATA27
MA_ADD1
MB_DATA19
MB_DQS_L5
M_A_DQ26
M_A_DQ24
M_A_A0
M_B_DQ18
M_B_DQ16
H24
R21
D24
AC25
MA_DATA26
MA_ADD0
MB_DATA18
MB_DQS_H4
M_A_DQ25
M_B_DQ17
F22
A21
AC26
MA_DATA25
MB_DATA17
MB_DQS_L4
F20
W12
M_A_DQS7
D20
F26
MA_DATA24
MA_DQS_H7
MB_DATA16
MB_DQS_H3
M_A_DQ23
C23
W13
M_A_DQS#7
M_A_DQS#6
M_B_DQ15
D18
E26
MA_DATA23
MA_DQS_L7
M_A_DQS[7..0]
8
MB_DATA15
MB_DQS_L3
M_A_DQ22
B22
Y15
M_A_DQS6
M_B_DQ14
M_B_DQ12
C18
A24
MA_DATA22
MA_DQS_H6
MB_DATA14
MB_DQS_H2
M_A_DQ21
F18
W15
M_B_DQ13
D14
A23
MA_DATA21
MA_DQS_L6
MB_DATA13
MB_DQS_L2
M_A_DQ20
M_A_DQS5
E18
AB19
C14
D16
M_A_DQS#[7..0]
8
MA_DATA20
MA_DQS_H5
MB_DATA12
MB_DQS_H1
M_A_DQ19
M_A_DQS#5
M_A_DQS#4
M_B_DQ11
E20
AB20
A20
C16
MA_DATA19
MA_DQS_L5
MB_DATA11
MB_DQS_L1
M_A_DQ18
M_A_DQ16
M_A_DQS4
M_B_DQ10
M_B_DQ8
D22
AD23
A19
C12
MA_DATA18
MA_DQS_H4
MB_DATA10
MB_DQS_H0
M_A_DQ17
M_B_DQ9
C19
AC23
A16
B12
MA_DATA17
MA_DQS_L4
MB_DATA9
MB_DQS_L0
2
2
M_A_DQS3
G18
G22
A15
MA_DATA16
MA_DQS_H3
MB_DATA8
M_A_DQ15
M_A_DQS#3
M_A_DQS#2
M_B_DQ7
G17
G21
A13
AD12
MA_DATA15
MA_DQS_L3
MB_DATA7
MB_DM7
M_A_DQ14
M_A_DQS2
M_B_DQ6
M_B_DQ4
C17
C22
D12
AC16
M_B_DM[7..0]
8
MA_DATA14
MA_DQS_H2
MB_DATA6
MB_DM6
M_A_DQ13
M_B_DQ5
F14
C21
E11
AE22
MA_DATA13
MA_DQS_L2
MB_DATA5
MB_DM5
M_A_DQ12
M_A_DQS1
E14
G16
G11
AB26
MA_DATA12
MA_DQS_H1
MB_DATA4
MB_DM4
M_A_DQ11
M_A_DQS#1
M_A_DQS#0
M_B_DQ3
H17
G15
B14
E25
MA_DATA11
MA_DQS_L1
MB_DATA3
MB_DM3
M_A_DQ10
M_A_DQ8
M_A_DQS0
M_B_DQ2
M_B_DQ0
E17
G13
A14
A22
MA_DATA10
MA_DQS_H0
MB_DATA2
MB_DM2
M_A_DQ9
M_B_DQ1
E15
H13
A11
B16
MA_DATA9
MA_DQS_L0
MB_DATA1
MB_DM1
H15
C11
A12
MA_DATA8
MB_DATA0
MB_DM0
M_A_DQ7
M_A_DM7
E13
Y13
MA_DATA7
MA_DM7
M_A_DQ6
M_A_DM6
M_A_DM4
C13
AB16
M_A_DM[7..0]
8
MA_DATA6
MA_DM6
M_A_DQ5
M_A_DM5
H12
Y19
MA_DATA5
MA_DM5
M_A_DQ4
H11
AC24
MA_DATA4
MA_DM4
M_A_DQ3
M_A_DM3
G14
F24
MA_DATA3
MA_DM3
M_A_DQ2
M_A_DQ0
M_A_DM2
M_A_DM0
H14
E19
MA_DATA2
MA_DM2
M_A_DQ1
M_A_DM1
F12
C15
MA_DATA1
MA_DM1
G12
E12
MA_DATA0
MA_DM0
<Core Design>
<Core Design>
<Core Design>
1
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU(2/4)_DDR
CPU(2/4)_DDR
CPU(2/4)_DDR
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
A-NOTE2.0-AMD
A-NOTE2.0-AMD
A-NOTE2.0-AMD
SA
SA
SA
Date:
Date:
Date:
Tuesday, September 26, 2006
Tuesday, September 26, 2006
Tuesday, September 26, 2006
Sheet
Sheet
Sheet
5
5
5
of
of
of
55
55
55
A
B
C
D
E
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